Description
The Common Hardware Group (CHG) at Cisco is looking for an ASIC Design and Verification Engineer to join their team. The successful candidate will be responsible for driving the definition, architecture, and design of high-performance ASICs. They will own complex or multiple functional areas, develop reusable code for future projects, and debug at ASIC, SW, and HW levels.
Responsibilities:
- Drives the definition, architecture, and design of high-performance ASICs
- Owns complex or multiple functional areas
- Develops reusable code for future projects
- Debugs at ASIC, SW, HW level
- Leads design and DV work by solving block-level issues and participates in chip-level issue resolution
- Drives reviews and recognizes areas of architectural concerns
- Defines new verification methodologies
- Helps in lab bring-up
- Leads code reviews at platform level
- Identifies, designs, and implements power-saving solutions
Minimum Qualifications:
- Bachelor's + 7 years of related experience, or Master's + 4 years of related experience, or PhD + 2 years of related experience
- Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools
Preferred Qualifications:
- Experience with dashboard management for regression, coverage, test list completion, and other DV statistics
- Post-silicon lab bring-up experience
- Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
- Experience with Linux, C/C++, and/or Python/Perl
- Experience in Networking
Benefits:
- Medical, dental, and vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away (vacation, holidays, sick time)
- Opportunities for career growth and professional development