Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years translating circuit concepts into physical silicon, and you understand that layout is not just about fitting shapes into a floorplan, it is about making decisions that affect performance, power, and manufacturability at every turn. A well-placed via or carefully routed power rail can mean the difference between a memory cell that works at corner conditions and one that fails in the field.
Responsibilities
- Design and develop custom layouts for Embedded Memory IPs, Standard Cells, and IO structures using proficiency with Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, and Calibre DRC/LVS verification tools.
- Optimize layout topologies for density, performance, power, and manufacturability across advanced process nodes.
- Collaborate with circuit designers and verification teams to ensure layouts meet electrical and physical design requirements
- Debug and resolve DRC, LVS, and antenna violations in complex hierarchical designs
- Develop and refine layout methodologies and automation flows to improve efficiency across the IP portfolio
- Participate in design reviews and provide technical feedback on layout strategies
- Maintain documentation of layout guidelines, design decisions, and process updates
The Impact You Will Have
- Deliver high-performance, high-density memory layouts that enable customers to meet aggressive PPA targets
- Reduce time-to-market for Foundation IP products by improving layout development efficiency
- Enable successful tape-outs by catching and resolving physical design issues early
- Contribute to layout methodology improvements that scale across multiple process nodes. The team develops Foundation IP solutions across multiple advanced technology nodes.
- Support Synopsys' position as the leading provider of silicon-proven Foundation IP
- Help customers achieve first-pass silicon success with layouts that meet manufacturing requirements
Requirements
- Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related field
- 2+ years of hands-on experience in custom IC layout design, with focus on memory compilers, standard cells, or analog/mixed-signal blocks
- Deep understanding of layout fundamentals including device matching, parasitic extraction, electromigration, and IR drop
- Proficiency with industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent
- Solid grasp of DRC/LVS verification flows and ability to debug complex rule violations
- Strong documentation and communication skills for cross-functional collaboration
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.