Senior Memory Post Silicon Qualification Engineer

NVIDIA leads groundbreaking work in AI, high-performance computing, and visualization , and the memory subsystem is one of the most consequential parts of every silicon program we ship.

We are hiring a Senior Memory Qualification Engineer inside the Silicon Co-Design Group who will own high-speed memory bring-up, characterization, and qualification on our flagship GPU, CPU and SoC programs.

What you will be doing

• Bring up high-speed memory interfaces (GDDR, LPDDR, HBM) on complex GPU, CPU and SoC silicon , from first power-on through full PVT characterization and productization.

• Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across the memory controller, PHY, and DRAM device , for the full matrix of capacities, speeds, and configurations we ship.

• Lead root-cause closure on the hardest multi-team memory failures , spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload , with reusable workarounds and productized fixes.

• Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation , with the guardrails to make the outputs trustworthy enough to gate qualification decisions.

• Partner with pre-Si architecture, design, and DV teams to translate new memory features into targeted post-Si validation plans, and feed post-Si learnings back into pre-Si methodology.

• Work across globally distributed teams , silicon design, PHY, PCB, firmware, software, DRAM vendors, and manufacturing partners , including counterpart engineers in Taiwan and other major hubs.

What we need to see:

• B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent experience), plus 10+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.

• Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM , training, calibration, IO tuning, timing margin, and vendor-to-vendor behavior differences , with at least one specific example of taking an ambiguous memory failure to root-cause closure with a productized fix.

• Strong hands-on lab fundamentals , oscilloscope, DMM, thermal chambers, protocol analyzers , combined with working knowledge of PCB stack-up, board layout, power planes, and SI/PI guidelines that show up as real memory issues.

• Demonstrated AI-driven workflow you built or scaled for memory characterization, margin analysis, or failure triage , with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate.

Benefits:

• Competitive benefits, flexible time off, and continuous learning
• Equity eligibility