Description
Join the Cisco Silicon One Front-End Design team, at the core of Cisco's silicon development.
You will be part of a team that covers the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
Your responsibilities will include:
- Writing and reviewing micro-architecture specifications
- Implementing RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
- Contributing to full chip integration, timing methodology, and analysis
- Collaborating with verification engineers to resolve bugs and achieve coverage closure
- Working with the physical design team to close timing and PnR issues
- Supporting design methodology evolution and best practices
- Performing debug, root-cause analysis, and post-silicon validation in the lab
To qualify for this role, you will need:
- B.Sc./M.Sc. in Electrical Engineering from a top university
- RTL design experience
- Familiarity with UVM and functional verification methodologies
Preferred qualifications include:
- Experience with MATLAB simulations and bit-exact modeling environments
- Familiarity with mixed-signal systems and environments
- Knowledge and hands-on experience with Clock Domain Crossing (CDC)
At Cisco, you're part of a team that's revolutionising how data and infrastructure connect and protect organisations in the AI era.