ASIC Physical Design Engineer

We are seeking an ASIC Physical Design Engineer to join our team. You will work on physical design from RTL to GSDII, including design quality check, synthesis, formal check, partitioning, constraint creation, async check, timing analysis, and fixing/signoff. You will collaborate with experts in various areas and drive physical-friendly design with multiple teams. You will work on the most advanced process/technology and the largest chip in the world.

Responsibilities:

• Perform STA for hierarchical design
• Create and validate constraints, timing budget
• Achieve timing closure for partition and full chip levels
• Handle special timing closure for IO, clock, and test timing
• Conduct synthesis, netlist quality check, and formal verification
• Implement chip partition and floorplan
• Create function ECO
• Develop and enhance entire timing closure flow from frontend to backend
• Automate flow development and methodology

Requirements:

• Master's degree in EE, CS, or Microelectronics with 1+ year of experience
• Project experience in IC design implementation
• Courses taken in circuit design, digital design
• Hands-on experience with EDA software from Synopsys (FC/DC/PT/Formality) and Cadence (RC compiler/Genus/LEC)
• Proficiency in Python, Perl, or TCL
• Excellent English reading and writing skills

Preferred qualifications:

• Proficient user of Perl, Python, or TCL
• Excellent English communication skills
• Good DFT design knowledge