Description
The Common Hardware Group (CHG) at Cisco delivers silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products.
As an ASIC DFT DV Technical Lead, you will work with front-end RTL teams and backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Key responsibilities:
- Develop thorough test plans and test benches to verify comprehensive Design-for-Test (DFT) architecture
- Collaborate with design, design-verification, and physical design teams to integrate and validate test logic
- Work on innovative hardware DFT and test strategy aspects for new silicon device models
- Mentor and guide DFT DV engineers and provide technical leadership across projects
Requirements:
- Bachelor's or master's degree in electrical or computer engineering
- At least 10+ years of experience
- Experience in developing detailed test plans and test benches for DFT verification
- Prior experience in test planning based on complex design specifications
- Testbench development using System Verilog
- Debugging experience using DVE/Verdi
- Scripting skills in Tcl, Python/Perl
Preferred qualifications:
- UVM and advanced System Verilog knowledge
- Knowledge about JTAG protocol, scan architecture, MBIST, and boundary scan