R&D Engineering, Director

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification, and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging state-of-the-art technologies like AI/ML, GenAI, and Cloud.

The Digital Methodology Center of Excellence (DMCoE) develops and deploys industry-leading methodologies that enable successful adoption of Synopsys TestMAX solutions and advanced Design-for-Testability technologies across the semiconductor ecosystem.

You are a recognized DFT expert with extensive experience architecting and deploying test solutions for complex ASIC and SoC designs. You possess deep knowledge of scan architectures, ATPG, test access infrastructures, and DFT standards, coupled with the ability to influence technical strategies across organizations.

Responsibilities

• Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
• Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
• Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
• Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
• Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
• Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.

The Impact You Will Have

• Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs.
• Drive measurable improvements in test quality, manufacturability, and silicon reliability.
• Influence next-generation TestMAX capabilities through direct customer engagement and technical leadership.
• Accelerate adoption of advanced standards-based test architectures across strategic customer accounts.
• Improve engineering productivity through methodology standardization, automation, and best-practice development.
• Establish Synopsys as the trusted advisor and technology leader in DFT and manufacturing test solutions.
• Contribute to breakthrough technologies powering AI, automotive, networking, and high-performance computing applications.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
• Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• Strong understanding of:
• Scan insertion and scan compression
• Hierarchical DFT methodologies
• ATPG and diagnosis
• Stuck-at, transition, path-delay, bridge, and cell-aware fault models
• Coverage analysis and optimization
• Test cost and pattern count reduction techniques
• Expertise with standards including:
• IEEE 1149.1 (JTAG)
• IEEE 1149.6 (AC JTAG)
• IEEE 1687 (IJTAG)
• IEEE 1500
• Experience developing and deploying:
• JTAG / TAP Architectures
• Boundary Scan Networks
• IJTAG Instrumentation Networks
• Embedded Instrument Access Solutions
• Expertise in deploying and integrating DFT IP including:
• Codec / Embedded Compression
• OCC (On-Chip Clock Controller)
• LBIST
• TAP Controllers
• JTAG and IJTAG Infrastructure
• TDR Networks
• IEEE 1500 Wrappers
• Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
• Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.

Benefits

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries