Senior Silicon Validation Methodology Engineer for Low-Power (LPWR)

NVIDIA Silicon Co-Design Group (SCG) is a multi-functional team that contributes to various stages of product development, from architecture to productization. We are seeking a Senior Silicon Validation Methodology Engineer for Low-Power (LPWR) to own the department's LPWR validation methodology across GPU, SoC, and CPU, from architecture to silicon to product.

Job Description:

As a Senior Silicon Validation Methodology Engineer for LPWR, you will own the architecture, design, and first-use of end-to-end LPWR validation methodology from silicon to product. This includes:

• Setting the department standard for LPWR validation that can be reused across a broad array of silicon products
• Defining what needs to be tested, why, and how, including coverage bounds, PVT/variability, test-time vs. schedule, signoff criteria, milestone playbooks, and SOL expectations
• Inventing and implementing new LPWR validation approaches that challenge current paradigms on performance, power, idle vs. active behavior, and corner-case coverage
• Setting LPWR validation strategy and policy across teams, including long-lead items that outlive a single execution cycle
• Driving cross-functional consensus with Architecture, Design, Firmware, and Software under conflicting PPA, coverage, latency, and schedule priorities
• Improving validation workflow at department scale by building and adopting automation, coverage metrics, pre-silicon to post-silicon correlation, and AI-enabled analysis

Requirements:

• Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience
• 8+ years of hands-on silicon validation methodology experience, with deep ownership of low-power architecture and design
• Proven record of creating new LPWR validation methods, tools, or signoff criteria that were adopted across multiple products or teams
• Expert debug of silicon LPWR issues and ability to deconstruct ambiguous failures into simpler, reusable validation and corrective approaches
• Demonstrated strong ability to set validation strategy under hard trade-offs and influence cross-functional consensus
• Strong AI-enabled skills and thinking

Nice to Have:

• Experience setting LPWR or power-management validation policy, playbooks, or signoff bars that other teams ran without you in the critical path
• Shipped methodology reuse across multiple chips, SKUs, or platforms, with measurable impact such as higher coverage, fewer debug loops, lower SOL, or faster bring-up