Senior Mask Layout Design Engineer

We are seeking a Senior Mask Layout Design Engineer to join our growing team of diverse individuals responsible for handling high-speed mixed-signal circuit designs.

Job Description:

As a Senior Mask Layout Design Engineer, you will perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, Analog to Digital converters, and ESD structures designs in sub-micron CMOS technologies using Cadence tools.

You will work cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Your responsibilities will also include taking part in floor planning, custom layout, and verifying against design rules and schematics.

Requirements:

• BSEE or equivalent experience
• Minimum of 5+ years proven experience in Mask and Layout Design
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Expertise with Cadence custom circuit design tools, particularly Virtuoso
• Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield
• Ability to work optimally in a team with good interpersonal skills, passion, and positive energy
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Knowledge of DRC and LVS checking flows, ability to customize decks