Physical Design Engineer

NVIDIA is seeking Physical Design Engineers to join its Networking Silicon engineering team. The team designs high-speed communication devices that deliver high throughput and low latency.

Job Responsibilities:

• Perform physical layout for full-chip level, integration, pinning, and bump route
• Collaborate with block owners and project managers to ensure high-quality convergence in all layout aspects
• Be responsible for chip layout from floorplanning to tape-out

Requirements:

• Electronics Engineer certificate or B.Sc. in Electrical Engineering
• 5 years of hands-on full-chip layout and physical verification experience
• Strong background in physical verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes
• Knowledge of scripting languages: TCL, Unix, and Shell
• Experience in Linux environments
• Familiarity with AI tools or a willingness to learn
• Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus)
• Familiarity with physical verification tools: Synopsys (ICV), Siemens (Calibre)
• Self-motivation, attention to detail, and good interpersonal skills

Preferred Qualifications:

• Experience in methodology definition/flow ownership of full-chip/place and route
• Great teamwork skills
• Ownership, self-learning skills, and ability to work autonomously