Description
This is a hybrid role that can be performed three days per week from our San Jose, CA office.
Meet the Team Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G, 800G and 1.6T+ bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP design, system design, package design, and module design.
Your Impact As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products.
You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products. You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.
You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.
Minimum qualification: Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
Experience in design, simulation and measurement of high speed ICs in at least 3 of the areas listed below:
- High Speed Serial Links utilizing serializers, deserializers, and data convertors.
- Modeling requirements for system link simulations
- High Performance Output Drivers
- High Performance Phase Locked Loops
- Efficient clock transmission/propagation.
- Opamps and Programmable Gain Amplifiers.
- Equalization techniques.
Preferred Qualifications Experience with electrical transceiver applications including backplane and cable communications.
- Experience in FinFET and GAA technologies.
- High-frequency layout experience including floorplaning (power/ground, digital/analog signal routing), passives components (inductors, transformers, and transmission-lins).
- Experience in design for manufacturability including characterization over PVT, electromigration analysis,self-heating, and IR drop analysis.
- Experience in laboratory validation including ESD practices/methodology and construction of test setups.
- Experience in design software including Cadence (Virtuoso), Specture/APS/SpectreX, layout validation tools (Virtuoso and Calibre), EMX, mixed-signal simulations in AMS, and Matlab.
Benefits:
- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness
- Non-exempt employees receive 16 days of paid vacation time per full calendar year
- Exempt employees participate in Cisco's flexible vacation time off program
- 80 hours of sick time off provided on hire date and each January 1st thereafter