Description
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.
Key Contributions:
- Manages the definition, architecture and design of high performance ASICs
- Owns applications or multiple complex functional areas
- Oversees reusable code and its applications
- Creates re-usable code that promotes efficiencies in new ways
- Defines verification strategies
- Coordinates with appropriate stakeholders to integrate into PD and DV flows
- Owns infrastructure and testing environments
- Leads and designs the building blocks of multiple channels
- Applies and drives the design methodology from conception to production
- Influences and collaborates with teams to ensure specifications and requirements are met
- Leads technical expertise of a physical design function
- Interfaces with vendors and design leads on full chip timing closure, PI, and PV
- Owns the full electrical planning and specifications of electrical interfaces
- Develops multiple solutions, first test vehicles and performs verification and validation
Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12+ years of experience.
- Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and SSN.
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,
- Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators.
- Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
- Scripting skills: Tcl, Python/Perl.