ASIC Package SI/PI Engineer

OpenAI's Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design.

Responsibilities

• Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production.
• Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces.
• Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers.
• Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI requirements.
• Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements, and translate them into actionable package layout guidelines.
• Perform package-level PDN analysis, including impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture.
• Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, high-speed I/O placement, and package routing architecture.
• Develop simulation methodologies and automation flows for early architecture exploration, design-space optimization, and repeatable SI/PI sign-off.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees

Requirements

• 5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design and package electrical design.
• Strong understanding of signal-integrity and power-integrity fundamentals, including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution.
• Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent.
• Experience with package layout environments such as Cadence APD/SIP, including the ability to review and modify package structures for SI/PI optimization.
• Experience developing automated design optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization.
• Strong communication skills and the ability to work effectively across ASIC, package, PCB, system, mechanical, thermal, power, validation, and manufacturing teams.