Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a passionate and detail-oriented ASIC DFT professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry.
Responsibilities:
- Lead and drive execution of scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex IP designs along with a team of talented DFT engineers.
- Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
- Analyze/resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
- Guide team/Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
- Use AI tools/flow for DFT tasks execution to improve the efficiency.
- Collaborate with cross-functional teams and central DFT methodology team to define and implement best practices for DFT methodologies and flows.
- Contribute to the continuous improvement of automation and design flows to boost efficiency and reduce turnaround time.
Requirements:
- BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.
- Past experience of technically leading a team for DFT execution of IP projects. Experience in effective collaboration and stakeholder management with program management, design/verification and design implementation teams.
- Proven experience in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
- Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
- Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
- Some experience of using AI tools for DFT tasks and other basic tasks (script generation/usage) to automate design and test flows.
- Basic understanding of digital logic design, and verification principles is also useful.
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.