Description
You are an experienced PHY and SerDes architect with deep knowledge of high-speed serial links. You will own the PHY architecture, define data-path and clocking architectures, lead calibration and adaptation strategies, allocate power, area, performance, and latency, develop block specifications, close the end-to-end link budget, and define architecture sign-off, modeling, observability, and silicon bring-up requirements.
You will define advanced 112 Gb/s and 224 Gb/s PAM4 PHY architectures, improve first-silicon success, reduce integration risk, and enable differentiated, high-performance interface IP for advanced silicon applications.
Requirements include strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links, expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain, deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration, and experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.
We offer comprehensive health, wellness, and financial benefits, including monetary and non-monetary offerings.