Description
Provide technical support and engineering solutions for advanced Physical Design implementation flows, helping customers successfully deploy leading-edge EDA technologies.
Work closely with semiconductor customers to debug, optimize, and improve Physical Design methodologies across the design cycle.
Collaborate with worldwide Application Engineers and R&D teams to reproduce customer issues, analyze root causes, and deliver timely solutions.
Drive technical engagements involving floorplanning, placement, optimization, CTS, routing, timing closure, and PPA improvement.
Conduct technical presentations, customer trainings, methodology reviews, and knowledge-sharing sessions.
Support adoption of Synopsys Physical Design solutions including Fusion Compiler, ICC2, and related implementation technologies.
Key Skills & Experience:
- 3+ years of experience in ASIC Physical Design, Design Implementation, or Application Engineering.
- Strong hands-on experience with Synopsys Fusion Compiler and/or IC Compiler II (ICC2).
- Solid understanding of Physical Design methodologies including Floorplanning, Placement, CTS, Routing, Timing Closure, DRC/LVS Closure, and PPA optimization.
- Good knowledge of STA, extraction, physical verification, and signoff methodologies.
- Experience with PrimeTime (PT), StarRC, IC Validator (ICV), DSO.ai, or AI-driven optimization technologies is a plus.
- Familiarity with Tcl, Perl, Python, or Shell scripting.
- Strong debugging, problem-solving, and customer-facing skills.
- Excellent communication skills in English.
- Passion for solving complex Physical Design challenges and enabling customer success.