Staff Application Engineer- Physical Design

You will be a Staff Application Engineer - Physical Design at Synopsys, working directly with customers to support their use of Synopsys physical design tools, including Fusion Compiler, ICC2, and Design Compiler.

Your expertise in physical design will help customers achieve PPA targets on advanced node designs. You will debug complex physical design issues, develop methodology recommendations, and collaborate with R&D, product management, and field teams to drive product adoption.

Key responsibilities include:

• Supporting customer engagements on Synopsys physical design tools
• Debugging complex physical design issues across the RTL-to-GDS flow
• Developing and delivering methodology recommendations tailored to customer design constraints
• Running benchmarks and proof-of-concept flows to demonstrate tool capabilities
• Collaborating with R&D, product management, and field teams to translate customer pain points into product requirements
• Presenting technical content to customer engineering teams and management
• Traveling to customer sites as needed to provide onsite support, training, and design reviews

The impact you will have includes:

• Accelerating customer tapeout schedules through targeted methodology improvements and tool optimization strategies
• Enabling successful adoption of Synopsys tools at key accounts
• Shaping product roadmaps by surfacing real-world customer challenges and advanced node requirements
• Building deep technical relationships with leading semiconductor companies
• Reducing customer support escalations by proactively addressing methodology gaps
• Contributing to the success of chips that will ship in millions of devices

Requirements:

• Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years
• Deep experience with RTL-to-GDS flows using industry-standard tools
• Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2
• Proficiency with static timing analysis tools, particularly PrimeTime
• Solid understanding of advanced node design challenges at 7nm and below
• Experience with logical and physical synthesis flows and AI-driven methodologies for optimization
• Excellent communication skills with the ability to present technical concepts clearly

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.