Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Sr Staff Engineer, you will be part of the Interface IP group in Mississauga, ON, a cross-functional team of analog and mixed-signal designers working on high-speed SerDes IP in the latest FinFET process nodes. The team operates with a full suite of industry-standard IC design tools supplemented by custom in-house automation supported by an experienced CAD and software team.
Key Responsibilities:
- Review SerDes standards and define transceiver architectures and analog sub-block specifications for high-speed NRZ and PAM4 IP.
- Develop advanced circuit solutions to improve power, area, speed, and silicon robustness.
- Collaborate with analog, digital, and layout teams to ensure efficient design, verification, and implementation.
- Guide physical layout to minimize parasitics, device stress, and process variation.
- Define and execute design and verification strategies using industry-standard simulation tools.
- Present technical results and design tradeoffs to internal teams, customers, and stakeholders.
- Document design features, test plans, and results clearly and accurately.
- Support electrical characterization, analyze customer silicon data, and contribute to post-silicon improvements.
- Assist the system team and develop automation to improve productivity and quality.
Impact:
- Drive innovation in high-speed analog and mixed-signal design for next-generation connectivity, computing, networking, and AI.
- Influence SerDes architecture and improve scalability, performance, and power efficiency across the IP portfolio.
- Strengthen product quality and reliability through rigorous design, verification, and documentation.
- Mentor team members and promote a culture of technical excellence and continuous learning.
- Help deliver integrated solutions that meet demanding customer requirements and support successful post-silicon results.
Requirements:
- M.A.Sc. with 8+ years or PhD with 6+ years of relevant analog/mixed-signal IC design experience.
- Strong background in circuit/system modeling, analog design, DSP, and communications theory.
- Proven experience with Multi-Gbps SerDes architectures, including TX, RX, equalizers, samplers, drivers, serializers/deserializers, PLLs, DLLs, bandgaps, regulators, oscillators, ADCs, and DACs.
- Experience with analog/digital co-design, calibration, adaptation, and timing handoff.
- Familiarity with ESD design, custom high-speed digital logic, and reliability considerations such as EM, IR, aging, and self-heating.
- Proficiency in schematic entry, physical layout, SPICE simulation, and Verilog-A modeling.
- Strong understanding of jitter, noise, signal integrity, parasitics, crosstalk, and design-for-reliability principles.
- Excellent communication, documentation, problem-solving, and attention-to-detail skills.
Team:
You will join the Interface IP group in Mississauga, ON, a cross-functional team of analog and mixed-signal designers working on high-speed SerDes IP in the latest FinFET process nodes.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.