Design Verification Staff Engineer

You are a seasoned Design Verification engineer with over a decade of experience in digital design, particularly in timing exceptions and constraint management.

As a Design Verification Staff Engineer at Synopsys, you will lead full-cycle deployments of Timing Constraints Management (TCM), VC SpyGlass, and VCS across strategic accounts in Taiwan's semiconductor industry. Your responsibilities will include:

• Debugging complex timing constraint issues, such as false path validation and clock-domain crossing verification
• Building automation scripts and reusable deployment methodologies in Tcl, Python, and Perl to improve customer productivity
• Delivering technical workshops and hands-on training on TCM constraint management and VCS simulation debug techniques
• Collaborating with R&D teams to escalate critical customer issues and shape product roadmaps
• Partnering with sales and product management to identify technical expansion opportunities within accounts

The ideal candidate will have:

• MS in Electrical Engineering, Computer Engineering, or equivalent technical discipline
• 10+ years of hands-on experience in digital design implementation, static timing analysis, RTL verification, or signoff methodologies
• Deep working knowledge of SDC constraints, timing exceptions, and timing closure flows
• Proven experience debugging timing correlation issues between simulation-based validation and STA tools
• Strong technical background in lint, CDC, RDC, and structural verification methodologies
• Proficiency scripting in Tcl, Python, Perl, or shell for automation and flow development

In this role, you will enable Taiwan semiconductor leaders to close timing on complex SoCs faster, reduce customer debug cycles, and drive adoption of VC SpyGlass across RTL verification teams.