SoC Verification Technical Lead

You will lead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables.

Key responsibilities include:

• Leading verification teams of 3-4 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios
• Developing verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve
• Integrating and deploying Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments
• Debugging complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams
• Identifying project risks early, proposing mitigation strategies, and communicating status and blockers to Synopsys management and customer stakeholders
• Driving methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption

The impact you will have includes:

• Directly determining whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems
• Mentoring engineers who will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements
• Preventing costly respins and post-silicon surprises for customers building chips in 5nm and below through early identification of design risks and verification gaps
• Reducing verification cycle time and improving coverage quality across dozens of SSG projects annually through methodology improvements
• Shaping how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows through direct customer engagement

Requirements:

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field with 5+ years of hands-on SoC, subsystem, or IP verification experience
• Deep technical expertise in UVM testbench development, coverage analysis, verification planning, and complex multi-domain debug
• Proven experience leading verification teams through full project cycles, including resource planning, task assignment, and delivery against customer schedules
• Strong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or DDR, and how they interact in real SoC architectures
• Hands-on proficiency with Synopsys VCS, Verdi or equivalent waveform analysis tools, and integration of third-party VIP into verification environments

Benefits include:

• Comprehensive medical and healthcare plans
• Time away programs including ETO and FTO
• Family support options like maternity and paternity leave
• ESPP to purchase Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries