ASIC Digital Design, Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise.

You are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.

Working on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.

Responsibilities

• Build and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors
• Write System Verilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios
• Develop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals
• Debug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes
• Implement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation
• Collaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations
• Run regressions, analyze results, and work toward coverage closure, documenting verification status and outstanding issues

The Impact You Will Have

• Ensure Synopsys IP cores are thoroughly validated before they reach customers building AI accelerators, automotive systems, and cloud infrastructure
• Reduce post-silicon bugs and customer escalations by catching design issues early through systematic verification and coverage analysis
• Contribute to faster IP release cycles by building reusable verification components and efficient test strategies
• Help maintain high-quality standards across Synopsys IP products, directly impacting customer success and product reliability
• Support the development of verification best practices and methodologies within the Bangalore team
• Enable design teams to iterate faster by providing clear, actionable feedback on functional correctness and edge case behavior
• Build verification infrastructure that can scale across multiple IP variants and protocol configurations

Requirements

• 4-8 years of hands-on experience in ASIC or RTL verification for IP cores or digital designs
• Understanding of verification planning, test case development, and coverage-driven verification concepts
• Working knowledge of UVM or similar verification methodologies, with experience building testbench components and writing test cases
• Solid System Verilog skills, including understanding of constrained random verification, coverage, and assertions
• Familiarity with at least one industry-standard protocol such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, USB or similar
• Experience debugging RTL simulations using waveform viewers and analyzing coverage reports to guide verification progress
• Experience with Perforce or similar revision control environment
• Basic scripting ability in Python, Perl, TCL, or shell scripting to support automation and regression management
• Ability to use AI tools like Cursor and GitHub Copilot for analysis, development, debugs and maximizing productivity.
• Have good communication skills, will be a team player, and will have good problem-solving skills.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries