Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are an experienced Analog Layout Senior Engineer with a strong background in custom layout design. You are passionate about technology and thrive in a collaborative environment. With at least 5 years of experience in custom layout, you are proficient with layout entry tools such as Cadence and Synopsys and layout verification tools like Mentor Calibre and Synopsys ICV. You possess a solid understanding of semiconductor fabrication processes and MOSFET fundamentals. Your expertise in high-speed layout techniques, ESD, Latchup, Antenna, and EMIR is a testament to your deep technical knowledge. Additionally, you have experience mentoring junior engineers and leading layout teams to achieve project goals. Your excellent English communication skills, team-oriented mindset, and self-motivation make you an ideal fit for our dynamic team.
Responsibilities:
- Working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
- Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
- Applying Analog Layout techniques to ensure design meets performance with minimum area and good yield.
- Building and enhancing layout flow for faster, higher quality design processes.
- Performing layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
- Conducting PERC verification for ESD/LUP checks.
- Completing all design quality checks and data quality checks.
- Collaborating with Place and Route engineers to integrate analog layouts into the top level.
- Working with the Package team to ensure the integration of top die and package.
- Participating in design reviews across the global team.
- Engaging in package design, including interposer and RDL design.
- Collaborating closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
- Joining research programs to implement new ideas for future products and flows.
- Leading a layout team to complete a full design block.
- Mentoring junior layout engineers or interns.
Requirements:
- BS in Electronics Engineering, Electromechanics, Telecommunications.
- 5+ years of experience in custom layout.
- Proficiency with layout entry tools: Cadence, Synopsys.
- Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
- Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
- Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
- Experience mentoring/leading junior layout engineers.
- Ability to write layout review presentations and layout verification reports.
- Good English communication skills.
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.