Description
The Common Hardware Group (CHG) at Cisco creates innovative hardware platforms central to the AI era. You will define, design, and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. You will contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products.
Responsibilities:
- Define, design, and verify ASIC and ASIC subsystems
- Contribute to a multi-disciplined engineering team
- Design, document, and develop ASIC subsystems for release in high volume and quality
- Help define the process, methods, and tools for design and implementation of complex developments
Minimum Qualifications:
- Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
- Prior experience with RTL development skills and experiences
- Prior experience with CDC/RDC concepts and relevant design implementation
- Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
- Prior experience with static glitch hazards and experience on the relevant analysis on synthesis optimized gate netlists
Preferred Qualifications:
- Experience on SDC constraints development
- Experience on VCS simulation SVA (SystemVerilog Assertions)
Benefits:
- Medical, dental, and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- 10 paid holidays per full calendar year
- 1 paid day off for employee’s birthday
- Paid year-end holiday shutdown
- 4 paid days off for personal wellness
- Non-exempt employees receive 16 days of paid vacation time per full calendar year
- Exempt employees participate in Cisco’s flexible vacation time off program
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- Optional 10 paid days per full calendar year to volunteer