Sr Staff Applications Engineer - ICV Runset Development

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes.

Responsibilities

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

The Impact You Will Have:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys.
• Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

Requirements

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-10 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail.
• A collaborative team player who fosters knowledge sharing and mentorship.
• Effective communicator, capable of translating technical concepts to diverse audiences.
• Adaptable and proactive, with a passion for continuous learning and innovation.
• Customer-focused, with a commitment to delivering high-quality solutions on time.
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.