Senior Silicon Power Engineer

NVIDIA is seeking a Senior Silicon Power Engineer to own power-feature productization on a flagship silicon program. The successful candidate will lead the effort across architecture, validation, firmware, software, and production teams to keep the program's power and low-power productization strategy clear, executable, and on track.

Responsibilities:

• Lead the effort across architecture, validation, firmware, software, and production teams to keep the program's power and low-power productization strategy clear, executable, and on track.
• Characterize and validate new power-saving features, debug silicon issues, and work with SW/FW teams to productize industry-defining capabilities.
• Resolve complex silicon issues through structured hypotheses, measurement plans, and root-cause closure , and codify the fixes as reusable methodology across programs.
• Design and deploy AI-enabled workflows to automate data analysis, metric extraction, trend checks, and report generation across multiple bring-ups , with explicit guardrails and measurable workflow impact.
• Serve as the key technical owner for multi-functional decisions, issues, and tradeoffs across power, thermal, performance, firmware, and schedule constraints.
• Partner with globally distributed teams , system architects, chip and board designers, SW/FW engineers, applications, reliability specialists, ATE engineers, and PMs , including counterpart engineers in India and other major hubs.

Requirements:

• BS + 5 years, or MS + 4 years, in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience), with a proven track record in post-silicon bring-up and validation of silicon power features on complex ASIC or SoC programs.
• Deep hands-on expertise in power-saving mechanisms, power characterization, tester-to-system correlation, and lab fundamentals (oscilloscopes, DMM, DAQ, debuggers) , with at least one specific example of taking an ambiguous power failure to root-cause closure with a productized fix.
• Strong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions, and a demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.
• Demonstrated AI-enabled workflow you built or scaled for silicon characterization or validation , with adoption beyond yourself, measurable workflow impact, and clear validation discipline, observability, and guardrails.

Nice to Have:

• Deep hands-on subsystem expertise across Windows and Linux low-power states, silicon power behavior, transistor/device physics, silicon reliability, and aging mechanisms , including original power-analysis methodology adopted by other programs.
• Silicon-level impact you personally drove , faster bring-up, stronger characterization coverage, better debug turnaround, or methodology improvements that reduced risk across programs, backed by artifacts, patents, or published technical work.
• Experience partnering deeply with a counterpart team in India or another major engineering hub , shared on-call, shared metrics, and shared culture across geographies.
• AI work that goes beyond personal-copilot use , agentic workflows, RAG-grounded debug assistants, ML-driven characterization analytics, or automated trend detection , deployed at team scope with adoption metrics