ASIC Physical Design Engineer (RDSS Intern)

By submitting your resume, you're expressing interest in our 2027 RDSS program.

As an ASIC Physical Design Engineer at NVIDIA, you'll work on the physical design of digital chips, focusing on high frequency, low power consumption, and multiple applications.

Responsibilities:

• Chip integration and netlist generation
• Synthesis
• RTL/netlist quality check
• Formal Verification
• Constraints creation and validation, timing budget
• Collaborate with the ASIC team to analyze and resolve special timing issues
• Cross-team collaboration for chip partitioning and floorplan implementation
• Work with PR engineers to achieve timing closure for both partition and full chip levels
• Achieve special mode timing closure (e.g., io, test, clock, async)
• Function eco creation
• Develop and improve the entire timing closure flow from frontend to backend
• Flow automation development for the above areas
• Methodology development in any of the above areas

Requirements:

• Master's degree in Electrical Engineering or Microelectronics
• Project experience in IC design implementation
• Courses taken in circuit design, digital design
• Hands-on experience with EDA software (e.g., Synopsys DC/PT/Formality, Cadence RC compiler/LEC)
• Proficiency in Python or TCL
• Proficient in English reading and writing