Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a seasoned RTL design leader with a strong record of driving complex ASIC digital subsystems from concept to silicon. You bring the technical depth to define architecture, translate requirements into clear specifications, and deliver high-quality, first-time-right RTL for robust, scalable subsystem designs.
What You Will Be Doing:
- Leading the subsystem lifecycle from requirements and architecture definition through release
- Developing subsystem architecture, functional specifications, and high-quality RTL micro-architecture
- Driving design quality through RTL linting, CDC, RDC, and close partnership with verification, DFT, and implementation teams
- Integrating standard protocols such as UCIe, Ethernet, UALink, and AMBA into subsystem designs
- Applying low power and DFT design methodologies at the architectural level
- Mentoring junior engineers and contributing to technical reviews and design excellence
The Impact You Will Have:
- Delivering high-performance digital IP subsystems that power next-generation silicon solutions
- Enabling first-time-right RTL, helping reduce verification cycles and accelerate time-to-market
- Strengthening subsystem quality, scalability, and interoperability through rigorous design practices
- Influencing architectural decisions that shape the future of digital IP design at Synopsys
- Contributing to a collaborative, innovative engineering culture through mentorship and technical leadership
What You Will Need:
- BSEE, BSCE, MSEE, MSCE, or an advanced degree, plus 8+ years of direct experience in RTL design and subsystem architecture for complex ASIC or SoC projects
- Strong expertise in RTL coding using Verilog/System Verilog, along with linting, CDC, RDC, and formal verification tools
- Experience with standard protocols such as UCIe, Ethernet, UALink, and AMBA
- Solid knowledge of low power design methodologies, DFT architecture, and the broader ASIC design flow
- Proven ability to lead cross-functional efforts from specification through silicon
Rewards and Benefits:
- Comprehensive medical and healthcare plans that work for you and your family
- In addition to company holidays, we have ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
- Save for your future with our retirement plans that vary by region and country
- Competitive salaries