Technical Engineering Intern - Design for Test (DFT) Internship

Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally.

As a DFT Intern Engineer, you will contribute to the development of high-quality semiconductor IP and SoC solutions while gaining invaluable hands-on experience in real-world chip development projects.

Your responsibilities will include:

• Supporting DFT Implementation and Verification: Assist in Design-for-Test activities including scan insertion, ATPG (Automatic Test Pattern Generation), test coverage analysis, and validation to ensure silicon testability and quality.
• Developing Automation Solutions: Create and deliver scripting and automation tools using TCL, Perl, Python, or Shell to improve engineering productivity and streamline DFT workflows.
• Collaborating on Chip Development Projects: Work alongside experienced engineers on innovative technologies powering data center, AI, mobile, and automotive applications, contributing to the successful delivery of trusted silicon solutions.
• Debugging and Problem-Solving: Analyze and resolve design and test-related issues, applying strong analytical skills to enhance design efficiency and manufacturing yield.
• Participating in Technical Reviews: Engage actively in team discussions, technical reviews, and project activities, sharing your ideas and learning from industry experts in semiconductor design and test methodologies.

Required Qualifications:

• Currently pursuing a final-year undergraduate or graduate degree in Electronics Engineering, Computer Engineering, Telecommunications, Electrical Engineering, or related disciplines.
• Basic understanding of CMOS and digital logic design fundamentals.
• Scripting experience with languages such as TCL, Perl, Python, or Shell.
• Strong analytical and problem-solving skills with a passion for semiconductor technologies.
• Good communication skills in English, both written and verbal.
• Self-motivated, eager to learn, with strong teamwork and collaboration abilities.

Preferred Qualifications:

• Basic knowledge of Design-for-Test (DFT) concepts, including Scan, ATPG, and JTAG.
• Familiarity with Linux/Unix environments.
• Experience with EDA tools such as Synopsys Design Compiler (DC), Fusion Compiler (FC), PrimeTime, TestMax, Verdi, or similar platforms.
• Participation in academic, research, or personal projects related to digital IC design or ASIC design.