Compute Electrical Engineer, Robotics

Compensation

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The salary range for this role is $318K – $485K, with generous equity, performance-related bonuses for eligible employees, and the following benefits:

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees
• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors.

About the Role

We’re looking for an Electrical Engineer to develop the AI inference compute systems that power OpenAI’s humanoid robots. This role combines compute architecture, high-speed digital design, onboard power electronics, and compact HDI PCB development.

Responsibilities

• Own compute hardware architecture and development, from component selection and schematic design through PCB layout, validation, and deployment.
• Design and integrate high-speed interfaces,including PCIe, DDR, Ethernet, MIPI, USB, and DisplayPort,balancing bandwidth, connectivity, power, and signal integrity.
• Develop onboard DC-to-DC conversion and power distribution to meet efficiency, transient-response, sequencing, and power-integrity requirements.
• Define HDI PCB stackups, dielectric materials, via structures, and routing strategies that balance electrical performance, manufacturability, reliability, and cost.
• Lead bench bring-up and validation, including test planning, high-speed interface characterization, power measurements, and debugging through verified resolution.
• Partner with thermal, mechanical, EMC, and software teams to integrate compute hardware into tightly constrained robotic systems.

Requirements

• Have 5+ years of experience developing compute hardware or similarly complex high-speed electronics, with demonstrated ownership of complete designs.
• Bring strong hands-on measurement and debugging skills, including practical experience with oscilloscopes, probing techniques, and interface validation.
• Understand high-speed digital interfaces deeply enough to make architectural tradeoffs and diagnose issues across hardware and software boundaries.
• Have strong signal-integrity and power-integrity fundamentals, a solid foundation in power electronics, and practical experience designing complex HDI PCBs.
• Can use a Linux shell, write simple shell scripts, connect over SSH, and perform basic Ethernet and network troubleshooting.
• Take initiative, turn ambiguous requirements into concrete engineering plans, and follow through to deliver working systems.

Preferred Qualifications

• Experience designing around AI inference SoCs or accelerators, including their power, memory, and communication architectures.
• Familiarity with how AI inference workloads map to silicon capabilities, including compute throughput (TOPS), DRAM bandwidth and capacity, and how workload requirements and DRAM technology choices affect achievable performance and performance per watt.
• Experience bringing compute hardware into production and resolving fabrication, assembly, or test issues with manufacturing partners.