ASIC-PD Engineer

The ASIC-PD team is seeking junior and senior engineers for physical design roles, focusing on RTL to GSDII, including design quality checks, synthesis, formal verification, partitioning, constraint management, asynchronous checks, timing analysis, and sign-off. You will collaborate with experts across various teams, including ASIC, P&R, DFT, SI, and ARCH. The position involves working on the most advanced process technology and the largest chip in the world.

Responsibilities

• Perform STA for hierarchical designs
• Create and validate constraints, manage timing budgets
• Achieve timing closure at partition and full-chip levels
• Handle special timing closures for I/O, test, clock, etc.
• Conduct synthesis, netlist quality checks, and formal verification
• Implement chip partitioning and floorplanning
• Create functional ECOs
• Develop and enhance timing closure flows from frontend to backend
• Automate flow development and methodologies

Requirements

• Master's degree in Electrical Engineering, Computer Science, or Microelectronics with 1+ year of experience
• Experience in IC design implementation projects
• Courses in circuit design and digital design
• Familiarity with EDA software from Synopsys (FC/DC/PT/Formality) and Cadence (RC Compiler/Genus/LEC)
• Proficiency in Python, Perl, or TCL
• Strong English reading and writing skills

Preferred Qualifications

• Advanced proficiency in Perl, Python, or TCL
• Excellent English communication skills