CAD Developer, IR, Timing and Physical Design Optimization

We are seeking a CAD Developer to join our ASIC-PD team, working on physical design from RTL to GSDII, including design quality check, synthesis, formal check, partitioning, constraint, async check, timing analysis, and fixing/signoff. You will work with experts in these areas, driving physical-friendly design with related teams, and focus on the most advanced process/technology and the biggest chip in the world.

Responsibilities

• Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
• Improve algorithms (in C++) for IR drop optimization, simulation.
• Own the whole process from discovery and invention of new optimization opportunities to developing solutions and working directly inside design teams to facilitate deployment.

Requirements

• BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience.
• Minimum 2+ years of relevant experience in CAD software and VLSI hardware design.
• Strength in both CAD software and VLSI design.
• Understanding of VLSI IR drop optimization or simulation and related concepts, including constraints, corner, CCSP, FSDB etc.
• Demonstrated ability in software development using C++.
• Strong communication and interpersonal skills.

Nice to Have

• Familiarity with RedHawk and typical design flows written in Perl, Tcl, and Python.
• C++14 or newer experience, such as lambdas and concurrency.
• Experience in high-performance software design including multithreading, distributed computing, efficient memory, and I/O use, etc.
• Experience in IR drop optimization, calculation.