R&D Engineering, Engineer

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

You are a passionate software engineer with a strong background in algorithms and system-level thinking. You enjoy solving complex problems and are driven to build scalable and efficient backend solutions for large-scale hardware systems.

Responsibilities

• Develop and optimize multi-FPGA partitioning algorithms for the ZeBu emulation compile flow, going beyond pure cut-size minimization
• Build timing-aware partitioning solutions that incorporate critical path timing criticality into partition cost models and optimization objectives
• Account for ZeBu clocking constraints,such as driver-clock-driven user clocks via multi-cycle paths,when evaluating partition quality and feasibility
• Design and enhance a more robust partitioning engine that reduces sensitivity to random initial solutions in traditional hMetis-based flows
• Apply analytical partitioning approaches to improve initial solution quality, stability, and reproducibility
• Work on constraint-aware partitioning for logic/memory resources, inter-FPGA connectivity, and timing-related partition constraints
• Collaborate closely with the FPGA P&R and runtime teams to validate partitioning decisions and support ZeBu platform sign-off
• Analyze partitioning bottlenecks and implement scalable, maintainable C/C++ backend components on Linux

The Impact You Will Have

• Improve emulation performance by making partitioning timing-aware, not just cut-size driven
• Increase partitioning robustness and reproducibility by reducing dependence on random initial solutions
• Improve partition quality and compile outcomes for large SoC designs through a more stable partitioning engine
• Enable successful ZeBu platform sign-off by delivering partitioning solutions validated with FPGA P&R and runtime teams
• Advance state-of-the-art emulation partitioning by combining classical graph partitioning with analytical optimization techniques

Requirements

• Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field
• Strong foundation in algorithms, data structures, and graph/hypergraph partitioning
• Experience with C/C++ and performance-oriented software development on Linux/Unix
• Knowledge of optimization techniques and partitioning algorithms (e.g., hMetis, multi-way partitioning, heuristic and analytical methods)
• Understanding of timing-aware optimization or willingness to develop expertise in timing-critical partitioning

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries