Description
We are seeking a skilled DPU Performance Validation Engineer to join our Network Silicon Engineering group. You will be responsible for debugging, analyzing, and validating the performance and functional behavior of current and future NVIDIA silicon devices.
Key Responsibilities:
- Learn and analyze the system-level operation of NVIDIA DPUs
- Debug and root-cause performance issues in pre-silicon environments across RTL, waveform traces, and multi-die system simulations
- Collaborate with design, verification, architecture, and performance modeling teams to isolate and fix issues
- Develop and improve validation methodologies for performance experiments and data collection
- Automate repetitive debug and validation tasks to scale coverage and efficiency
Requirements:
- B.Sc. in Electrical Engineering, Computer Engineering, or equivalent
- 3+ years of experience in ASIC development/validation
- Strong background in ASIC debug, including reading RTL, analyzing waveforms, and root-causing functional or performance issues
- Hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems)
- Proficiency with Python and C/C++ in a Linux environment
- Excellent interpersonal skills and ability to work optimally as part of a multi-functional team
Preferred Qualifications:
- Expertise in performance modeling, traffic generation, or architecture studies
- Experience with modern interconnects and protocols (e.g., PCIe, Ethernet, CHI)
- Familiarity with emulation platforms (e.g., Palladium, Veloce, FPGA prototyping)
- Passion for experimental work, data-driven validation, and creative problem solving