ASIC Design Engineer, High Speed IO

NVIDIA is seeking an RTL Design engineer for its High Speed IO IP's deployed in Automotive chips. As a key designer, you will be responsible for UFS/Ethernet/PCIE/USB IP's of next-generation chips, requiring strong digital design and verification fundamentals.

The role involves understanding specific protocol concepts and features, making architectural trade-offs based on feature/performance/power requirements, analyzing system implications, and coming up with the micro-architecture. You will implement RTL, drive verification, close timing, and support silicon validation.

Key responsibilities include:

• Owning micro-architecture and RTL development of design modules
• Micro-architecting features to meet performance, power, and area requirements
• Collaborating with HW architects to define critical features
• Partnering with verification teams to verify implemented features
• Working with timing, VLSI, and Physical design teams to ensure design meets requirements

Requirements:

• BTech/MTech in EE, ECE, or similar, with 2+ years of experience in crafting complex Units and CPU/micro-controller-based Sub-systems
• Knowledge of HSIO standards, protocols, and architectures of modern SOC's
• Excellent influencing skills for collaboration with cross-cultural, multi-geography, and matrixed teams
• Good debugging, analytical, and problem-solving skills
• Great interpersonal skills and ability to work as an excellent teammate
• Exposure to AI tools like Claude and Cursor is a plus

NVIDIA offers highly competitive salaries and a comprehensive benefits package. Learn more at www.nvidiabenefits.com/