Description
NVIDIA's System-on-Chip (SoC) group is seeking a motivated Padring Verification Engineer to develop scalable verification methodologies and deliver high-quality padring verification results for complex GPU and Tegra SoCs.
In this role, you will create verification methodologies, tools, and automation for padring RTL integration, connectivity verification, and chip assembly. You will also execute padring verification and padring connectivity signoff for GPU and Tegra projects, applying and continuously improving the methodologies you develop. The work includes verification of DFT-related padring logic, such as boundary scan and test-access connectivity. You will collaborate closely with RTL, DFT, Physical Design, CAD, Package Design, and Software teams.
Responsibilities:
- Develop and maintain scalable padring verification methodologies, infrastructure, and automation for RTL integration, connectivity verification, and chip assembly.
- Execute padring verification and padring connectivity signoff for GPU and Tegra projects; analyse results, debug failures, and drive issues to closure.
- Verify DFT-related padring logic, including boundary scan, test-access connectivity, control/configuration logic, and integration correctness.
- Define verification plans and develop assertions, checkers, testbenches, coverage goals, and regressions for padring functionality and SoC integration.
- Build tools and flows that identify padring integration issues early, improve debug efficiency, and strengthen verification signoff quality.
- Partner with DFT, RTL, Physical Design, CAD, Package Design, and Software teams to resolve complex issues and meet project milestones.
- Apply AI-assisted approaches to padring verification, methodology automation, and debug challenges.
Requirements:
- MS in Computer Engineering, Electrical Engineering, or equivalent practical experience.
- 1–8 years of experience in ASIC/SoC design, RTL verification, SoC integration, or methodology development.
- Strong understanding of RTL and SoC verification concepts, including simulation, formal checks, assertions, coverage, regressions, debug, and signoff.
- Familiarity with DFT concepts, particularly boundary scan, JTAG/test-access mechanisms, scan/test modes, or padring DFT integration.
- Experience creating verification environments, checkers, or automation for SoC- or subsystem-level designs.
- Proficiency in Python, Perl, or other industry-standard scripting languages.
- Excellent analytical, problem-solving, communication, and cross-functional collaboration skills.