Description
Boeing Space, Intelligence & Weapons Systems is seeking multiple ASIC/FPGA Digital Design Engineers to join their team in El Segundo or Huntington Beach, CA. The role involves supporting ASIC, FPGA, or mixed ASIC/FPGA developments in an aerospace environment.
Engineers will contribute to advanced aerospace and defense programs, including next-generation satellite and space systems, modules supporting NASA missions, and commercial and military aircraft platforms. The team expertise spans requirements development, architecture activities, RTL design, ASIC development, FPGA implementation, timing analysis, verification collaboration, integration support, and system-level troubleshooting.
Responsibilities:
- Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment
- Contribute to requirements development, refinement, interface definition, conceptual architecture activities, and traceability efforts
- Develop HDL / RTL for ASIC, FPGA, and SoC systems
- Compile, simulate, debug, and troubleshoot digital designs
- Perform and/or support synthesis, implementation, constraints development, timing closure, and tool execution activities
- Collaborate with verification teams to support simulation, debug, coverage, and integration goals
- Apply timing concepts, CDC fundamentals, and integration considerations
- Support broader system troubleshooting and integration activities
- Communicate technical status, risks, dependencies, and tradeoffs proactively
Lead, Level 4:
- Support subsystem ownership activities
- Mentor others
- Lead larger technical efforts, integration activities, or technical teams
Senior, Level 5:
- Provide technical leadership
- Support architecture direction and broader technical ownership
- Lead teams, subsystem efforts, and cross-functional initiatives
Basic Qualifications:
- Bachelor of Science degree in Engineering (Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications
- 9+ years of experience with FPGA, ASIC, or SoC digital design; or a BS/MS and 7+ years of FPGA, ASIC, or SoC digital design experience
- Experience with HDL development, simulation, debug, and synthesis
- Strong digital design fundamentals
- Experience troubleshooting digital systems
- Understanding of timing fundamentals and CDC concepts
Preferred Qualifications:
- 14+ years of related engineering experience for Senior, Level 5
- Experience with requirements development and traceability
- FPGA implementation including constraints and timing closure
- Static timing analysis experience
- Verification collaboration experience
- High-speed interfaces, processor integration, memory subsystems, or SoC integration
- Mentoring or technical leadership exposure
Benefits:
- Competitive base pay and variable compensation opportunities
- Health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs
- Paid and unpaid time away from work
Salary Range:
- Lead, Level 4: $146,200 - $197,800
- Senior, Level 5: $164,900 - $223,100