Senior ASIC Physical Design Engineer, Netlisting

NVIDIA is seeking a Senior ASIC Physical Design Engineer, Netlisting to join their team. The successful candidate will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects.

Responsibilities:

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
• Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
• Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
• Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise and in-depth knowledge of industry standard EDA tools in related fields.
• Proficiency in programming and scripting languages, such as Perl, TCL, Make, Python, etc.

Benefits:

• Equity
• Benefits