Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams.
Responsibilities:
- Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.
- Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams.
- Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
- Run and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.
- Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
- Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
- Use Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
- Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
- Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.
Requirements:
- Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
- 8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
- Strong hands-on experience in:
- Constraints development/validation (SDC)
- STA signoff across modes/corners, including MMMC concepts
- Timing closure debugging and ECO validation
- Power analysis/support (PrimePower / PT-PX exposure preferred)
- Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
- Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
- Strong scripting skills in TCL (required) and Python/Perl (preferred).
- Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.