Applications Engineering, Sr Staff Engineer

We are seeking an experienced Physical Verification Specialist with a passion for cutting-edge technology and a deep understanding of physical verification and its applications. As an Applications Engineering, Sr Staff Engineer, you will work closely with customers to understand their Physical Verification challenges and provide timely solutions. You will support the sale and adoption of IC Validator product to enhance customer performance, quality, and development timelines.

Key responsibilities include:

• Providing expertise in Physical verification for advanced node designs.
• Managing multiple customer activities, including product demonstrations, evaluations, and competitive benchmarks.
• Conducting training sessions, resolving technical issues, and offering technical account management.
• Collaborating with account teams to develop tailored solutions that address customer needs and challenges.
• Creating flows in TCL/Python as well as DRC/LVS/FILL/PERC PXL/Python runset writing.
• Working closely with R&D, Product Engineering, and Sales to drive tool and customer success.

The impact you will have:

• Enable customers to tape out advanced node designs faster and with higher confidence by delivering verification solutions that catch real issues early.
• Drive IC Validator adoption and revenue growth by proving tool performance, quality, and workflow advantages in competitive evaluations.
• Reduce customer escalations and support load by building reusable flows, runsets, and documentation that teams can deploy independently.
• Influence IC Validator product roadmap by channeling customer feedback, use cases, and technical gaps directly to R&D and Product Engineering.

Requirements:

• BS or MS degree in Electronic Engineering, Computer Science with knowledge of VLSI and device component or similar.
• Good scripting/programming skills are required, with a preference for shell scripting like Python, TCL, Perl.
• 7+ years of hands-on, industry experience in physical verification flows (LVS/DRC/FILL/PERC) and good understanding of runset development.
• Experience of EDA tool products such as IC Validator, Calibre or Pegasus.
• Understanding of backend physical design flows (FC/Innovus), Custom layouts (Custom Compiler/Virtuoso layout) and PEX flows.
• Passion to learn, poised under high pressure, pro-active with high efficiency, natural curiosity to learn new technologies and demonstrate good debug and problem-solving skills.
• Capability to produce adequate technical documentation.
• Exceptional communication, presentation, organizational and interpersonal skills.