Description
You will define, design, and verify ASIC and ASIC subsystems for deployment in various Cisco platforms. As part of a multi-disciplinary engineering team, you will contribute to meeting power, performance, and area goals for products. Your responsibilities include:
- Architecting block, cluster, and top-level DV environment infrastructure
- Developing DV infrastructure from scratch
- Maintaining and improving existing DV environments
- Creating test plans and tests for qualifying designs at various levels
- Ensuring complete verification coverage through code and functional coverage
- Qualifying RTL quality with Gate Level Simulations on netlist
- Collaborating with designers, architects, and software teams to address issues during post-silicon bring-up
- Supporting testing of designs in emulation
- Leading the ASIC bring-up process
The ideal candidate will have:
- A Bachelor's degree with 7+ years of relevant ASIC design verification experience or a Master's degree with 5+ years of experience
- Proficiency in ASIC verification using UVM/System Verilog
- Experience building test benches from scratch and working with System Verilog constraints, structures, and classes
- Scripting experience with Perl and/or Python
Preferred qualifications include:
- Experience with forwarding logic, parsers, or P4
- Familiarity with Veloce, Palladium, Zebu, or HAPS
- Knowledge of formal verification tools
- Experience with protocols such as PCIe, Ethernet, RDMA, or TCP