R&D Engineering, Sr Engineer

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

You will work on standard cell libraries that power advanced node designs across the semiconductor industry. The libraries you characterize will be used in real tapeouts, and the quality bar is not negotiable.

Responsibilities

• Characterize and model standard cell libraries for advanced technology nodes, generating Liberty files including NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and EM models
• Handle characterization across a wide range of cell types: combinational, sequential, clock gating, synchronizers, retention, level shifters, power gating, always-on, filler, and decap cells
• Debug and resolve correlation issues between characterization results, static timing analysis, and SPICE simulations, working across tool flows to identify root causes
• Execute QA checks, regression analysis, and release validation to ensure library deliverables meet quality and accuracy standards before they ship
• Drive methodology improvements and automation initiatives that make characterization flows faster, more reliable, and easier to maintain across multiple projects
• Coordinate project execution timelines, manage deliverables, and communicate status across cross-functional teams including design, verification, and product engineering
• Support library releases by validating models against design rule checks, performing sanity testing, and ensuring documentation is complete and accurate

The Impact You Will Have

• Enable accurate timing closure for advanced node designs by delivering high-quality Liberty models that designers and STA tools depend on
• Reduce correlation gaps between characterization and silicon behavior, improving predictability and reducing costly respins for customers
• Accelerate library development cycles by building automation and improving characterization flows that scale across multiple technology nodes
• Increase library quality and reliability through rigorous QA, regression testing, and validation processes that catch issues before release
• Support successful tapeouts by ensuring standard cell libraries meet performance, power, and area targets across all operating conditions
• Contribute to methodology evolution by identifying gaps, proposing solutions, and implementing improvements that benefit the entire characterization team
• Help Synopsys maintain its leadership in library IP by delivering models that meet the precision and robustness requirements of cutting-edge semiconductor designs

Requirements

• Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field
• 2+ years of hands-on experience in standard cell library characterization and Liberty modeling
• Strong understanding of Liberty file formats including NLDM, CCS, ECSM, and advanced modeling constructs like AOCV, POCV, and aging models
• Experience characterizing multiple cell types: combinational, sequential, clock gating, level shifters, retention, or power management cells
• Solid grasp of SPICE simulation, timing analysis concepts, and correlation methodologies between characterization tools and STA flows
• Proficiency in scripting languages like Python, Tcl, or Perl for automation, data analysis, and flow development
• Experience with industry-standard characterization tools and STA platforms is a strong plus