Senior Circuit Characterization Engineer

NVIDIA's Silicon Co-Design Group is seeking a Senior Circuit Characterization Engineer to define and drive post-silicon circuit setting and performance across NVIDIA's GPU and SoC product families.

You will own the characterization of analog, digital, and mixed-signal circuits from first silicon through production , translating lab measurements into design improvements, guardband recommendations, and product-shipping decisions.

Responsibilities:

• Own Silicon Circuit bringup from first power on through production to optimize performance, power, yield, and quality for the world's fastest products across process, voltage, and temperature corners.
• Drive circuit characterization for critical on-die circuits including SRAM, PLL/DLL, clock distribution, voltage regulators, I/O interfaces, and on-die sensors , correlating measured silicon behavior with pre-silicon simulations to close the design loop.
• Design experiments, execute test plans, and build models that isolate circuit-level bottlenecks.
• Lead multi-functional root-cause closure across architecture, design, validation, software/firmware, power and thermal, reliability, ATE, product management, manufacturing, and operations, own fixes through confirmation.
• Analyze production-silicon data across PVT corners and binning populations to quantify guardbands, yield trade-offs, and circuit optimization opportunities that feed directly into product definition and future architecture decisions.
• Establish reusable automation, data analysis pipelines, and visualization tools that improve characterization coverage, execution efficiency, and debug velocity across simultaneous product.

Requirements:

• BS or MS degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of hands-on experience in post-silicon circuit characterization, silicon bring-up, or circuit validation on complex SoC or GPU products.
• Deep understanding of analog, digital, and mixed-signal circuit behavior , including SRAM, PLL, clock networks, voltage regulators, I/O circuits, and on-die sensors.
• Hands-on lab proficiency with oscilloscopes, spectrum analyzers, DAQ systems, source meters, high-speed probing, and tester-to-system correlation workflows.
• Strong background in power supply and substrate noise analysis , chip- and board-level dI/dt characterization, PDN impedance, droop measurement, and mitigation techniques.
• Proficiency in Python and scripting for automation, data analysis, and tool development; familiarity with C/C++ is a plus.
• Excellent problem-solving skills and a collaborative mindset , demonstrated ability to drive alignment across multi-site, cross-functional teams including offshore engineering organizations.

Nice to Have:

• Experience characterizing circuits at advanced process nodes on large-scale GPU or datacenter SoC products.
• Background in on-die noise measurement methodology , NMEAS, worst-case noise test development, noise watermarking, or Bayesian/ML-driven characterization optimization.
• Familiar with product binning methods, frequency-voltage optimization, guardband analysis, and statistical techniques for characterization data at scale.
• Experience with pre-silicon circuit simulation tools (SPICE, timing analysis) and silicon-to-simulation correlation workflows that close the loop between design and characterization.
• Explore creative ways to integrate AI insights into continuous improvement analysis, debug, workflow, utilize AI-driven method for silicon circuit optimization.