Description
We are looking for an ASIC Front-end Design engineer to join our team. As an ASIC Front-end Design engineer, you will be part of a fast-paced team responsible for delivering high-speed ASICs for large, complex systems.
Responsibilities:
- Define and architect high-performance blocks for the latest, most advanced networking ASICs
- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
- Collaborate with the verification team in the development of the testplan and assist in debugging test failures
- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Requirements:
- Strong Verilog RTL coding skills
- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
- Knowledge of high-performance memory subsystems
- Knowledge of multi-domain clock synchronization and high-speed serial interfaces
- Strong problem-solving and ASIC debugging skills
- Excellent written and verbal communications skills
- MSEE or BSEE is required