Senior Circuit Timing Engineer

We're seeking a Senior Circuit Timing Engineer to join our team. You'll work on groundbreaking processor design in deep submicron technologies, collaborating with a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.

Responsibilities:

• Participate in processor design in deep submicron technologies
• Work with a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions
• Drive timing analysis and signoff of custom circuit macros (digital, semi-custom, and analog mixed-signal)
• Validate timing of custom circuit designs using STA tools, including Nanotime, PrimeTime, Tempus, and various SPICE simulation tools
• Collaborate with cross-functional teams to improve power, performance, area, and reliability of NVIDIA's next-generation products through custom circuit solutions and detailed transistor-level analysis
• Develop timing models and methodology for innovative and unique custom macro designs
• Perform transistor-level circuit design and timing, schematic entry, and layout delivery
• Integrate AI/ML techniques directly into the design process and methodology
• Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, and timing ECO implementation

Requirements:

• BSEE/MS preferred in Electrical, Computer Engineering, or equivalent experience
• 6+ years of digital circuit design experience for Masters and 8+ years for Bachelors
• Excellent understanding of deep submicron process issues and digital circuit design techniques
• Expertise and in-depth knowledge of industry-standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools
• Hands-on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure
• Proven experience in timing constraints generation and management
• Hands-on experience in design and analysis of low-power circuits (power gating, decaps, multi-vt, etc.) is a plus
• Expertise in analysis and fixing of timing paths through ECOs, including crosstalk and glitch noise
• Solid understanding of extracted timing models and the usage of .libs in Primetime
• Knowledge of process variation effect modeling and experience in design convergence in multi-GHz deep submicron technology

Nice to Have:

• Proven ownership and hands-on experience across the entire silicon design flow, from micro-architecture and RTL design to back-end execution
• Proven capability in Post-Silicon characterization and debug, ensuring designs meet performance targets in hardware
• Track record of independently driving and delivering complex features from conception through tape-out and validation
• Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.