Description
We are seeking a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis.
Key responsibilities include:
- Support DFT implementation for ASIC / SoC blocks and subsystems
- Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
- Run DFT rule checks and debug scan, clock, reset, and test-mode issues
- Generate and validate ATPG patterns for stuck-at, transition, and other required fault models
- Analyze test coverage, pattern count, compression results, and ATPG reports
- Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
- Work with RTL and verification teams to ensure DFT requirements are correctly implemented
- Support block-level and full-chip DFT integration activities
- Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
- Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
- Support silicon debug, diagnosis analysis, and yield-learning activities as needed
- Document DFT implementation results, known issues, waivers, and signoff status
The starting salary range for this position is $155,000.00 to $222,600.00.
Benefits include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.