Layout Design, Manager

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years in the physical layout trenches of SRAM development, and you know that the difference between a memory that meets PPA targets and one that requires three more spins is usually a layout decision made during floorplanning. You understand how bitcell density, array routing, and peripheral placement affect yield, performance, and power in ways that do not show up in early simulations. You have debugged enough DRC violations, LVS mismatches, and EM/IR failures to recognize patterns before they become blockers.

Managing people energizes you because you want your team to have the support, clarity, and technical direction you wish you had earlier in your career. You know how to balance project timelines with technical quality. You can translate a vague requirement from a memory architect into a concrete layout task, and you can explain a complex parasitic issue to a project lead without losing them in the details.

At Synopsys, you will lead a team building embedded memories and memory compilers that ship in real products across advanced process nodes.

Responsibilities

• Lead a team of SRAM memory layout engineers through the full development cycle, from initial floorplanning and resource allocation to physical verification signoff and product release
• Own layout execution for memory arrays, bitcells, peripheral circuits, power distribution networks, and complete memory instances, ensuring they meet PPA, reliability, and manufacturability targets
• Drive resolution of complex physical design challenges including DRC, LVS, ERC, antenna violations, EM/IR analysis, routing congestion, and parasitic extraction issues across advanced FinFET and GAA nodes
• Manage project schedules, resource allocation, technical dependencies, and risk mitigation across multiple concurrent memory compiler and embedded memory development efforts
• Collaborate directly with circuit design, memory architecture, characterization, CAD tool development, physical verification, process technology, and foundry engineering teams to align layout execution with product requirements
• Build and improve layout methodologies, automation scripts, design reuse frameworks, and standardization practices that increase team efficiency and reduce development cycle time
• Mentor engineers, establish technical best practices, conduct performance reviews, support hiring and onboarding, and grow the technical capability of the layout organization

The Impact You Will Have

• Deliver embedded SRAM memories and memory compiler products that meet aggressive PPA targets and enable customer tapeouts on schedule
• Reduce layout development cycle time and improve design quality through methodology improvements, automation, and reuse strategies that scale across multiple projects
• Build a high-performing layout team with strong technical depth, clear career growth paths, and the ability to handle increasing complexity at advanced nodes
• Resolve critical physical design issues that unblock product releases and prevent costly respins or yield losses
• Strengthen cross-functional collaboration between layout, circuit design, and verification teams, reducing miscommunication and rework
• Establish layout best practices and design standards that improve consistency, quality, and knowledge transfer across the memory IP organization
• Enable Synopsys memory IP customers to achieve their performance, power, area, and time-to-market goals by delivering robust, manufacturable memory solutions

Requirements

• Bachelor's or master's degree in electrical engineering, Electronics, Microelectronics, or a related field
• 7+ years of hands-on experience in SRAM memory layout development, including work on bitcells, arrays, peripheral circuits, and full memory integration
• Deep understanding of SRAM architecture, memory compilers, and how layout decisions affect performance, power, area, yield, and reliability
• Strong working knowledge of DRC, LVS, ERC, antenna checks, EM/IR analysis, parasitic extraction, and advanced-node layout constraints
• Demonstrated experience leading engineering teams or managing complex technical projects with multiple stakeholders and dependencies
• Proficiency with industry-standard custom layout tools and physical verification flows, experience with layout automation and scripting is a plus
• Experience with SRAM memory compiler development across multiple process technologies and advanced FinFET or GAA nodes is a plus