Senior Analog Layout Design Engineer

NVIDIA's Analog Layout design team is looking for a Senior Analog Layout Design Engineer to handle high-speed mixed-signal circuit designs.

The successful candidate will perform physical layout for mixed-signal functions like PLL's, high-speed I/O circuits, SerDes, general I/O's, and ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

Responsibilities:

• Perform physical layout for mixed-signal functions
• Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
• Floor planning, custom layout, and verifying against design rules and schematics, EM/IR analysis

Requirements:

• Minimum of 5 years of relevant mask analog layout experience
• An Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering
• Proven understanding of analog circuit layout concepts in submicron CMOS and FinFet technologies
• Expertise with Cadence custom circuit design tools, particularly Virtuoso
• Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre
• Good interpersonal skills, enthusiasm, and positive energy

Nice to have:

• Proficiency in scripting languages like Python, Skill
• Knowledge of DRC and LVS checking flows, EM/IR tools, ability to customize DRC and LVS decks