Layout Design , Sr Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years in the trenches of layout design, working at nodes where every micron matters and where a floorplan decision made in week one determines whether your PHY meets timing, power, and area targets six months later. You know the difference between a layout that passes DRC and one that actually survives EMIR, latch-up, and real-world ESD events, and you have debugged enough tapeout issues to spot trouble before it becomes a showstopper.

What You'll Be Doing

• Lead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies
• Drive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks in high-speed memory interfaces
• Own effort estimation, schedule planning, and execution for layout projects, coordinating across design, verification, and customer engagement teams
• Mentor junior layout engineers on deep submicron effects, DFM best practices, and advanced layout techniques while challenging senior engineers to deliver higher quality on tighter timelines
• Conduct layout reviews, manage quality checks using Calibre and internal flows, and drive LEF generation, bond-pad layout, IO frame design, and release processes
• Translate PHY-level customer requirements into actionable layout constraints and work directly with customers to resolve pitch, area, and integration challenges
• Stay hands-on, jumping into critical layout tasks when schedules tighten or technical problems require deep expertise to unblock the team

The Impact You Will Have

• Your leadership will directly shape the performance, power, and area of memory PHY IP used in flagship SoCs across hyperscale data centers, AI training systems, and mobile platforms
• The floorplans and layout techniques you establish will become the foundation for future generations of DDR and HBM IP, influencing how Synopsys scales to next-node technologies
• Your mentorship will build a stronger, more capable layout team that can tackle increasingly complex process nodes and customer requirements with less escalation
• The quality and turnaround time improvements you drive will accelerate customer tapeouts and reduce costly respins, strengthening Synopsys relationships with top-tier semiconductor companies
• Your ability to translate ambiguous customer specs into executable layout plans will reduce integration risk and improve first-pass success rates for memory subsystems
• The cross-functional collaboration you foster between layout, design, and verification will break down silos and make the entire PHY development process more efficient
• Your hands-on problem solving during critical project phases will keep schedules on track and ensure that hard-won layout optimizations actually make it into silicon

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
• 8+ years of hands-on layout design experience in deep submicron CMOS technologies, with direct exposure to 7nm or below
• Demonstrated ability to lead layout projects from floorplan through tapeout, including effort estimation, resource planning, and cross-functional coordination
• Deep technical expertise in layout matching techniques, ESD design, latch-up prevention, PERC/EMIR analysis, DFM rules, LEF generation, and IO frame layout
• Strong understanding of FinFET and GAA process effects, including fin quantization, middle-of-line routing constraints, and advanced node design rules
• Experience working with memory PHY IP (DDR, HBM, LPDDR, or similar high-speed interfaces) and translating customer requirements into layout constraints is a strong plus
• Proficiency with Cadence Virtuoso, Calibre, and other industry-standard layout and verification tools

Rewards and Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries