Senior System Integration and Validation Engineer

The Silicon Co-Design Group (SCG) at NVIDIA is seeking a Senior System Integration and Validation Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs.

Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping.

Responsibilities:

• Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs , feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.
• Lead debug of the hardest cross-stack issues , logic, signal integrity, power delivery, firmware, and software interaction , and drive them to root cause with reusable workarounds and productized fixes.
• Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.
• Design and deploy AI-enabled debug and validation workflows used by the team , with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.
• Translate complex silicon and system risk into decision-ready options for technical and executive audiences , without padding or hand-waving.
• Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering , including counterpart engineers in India and other major hubs.
• Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.
• Find critical silicon and platform issues before they reach the customer , by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens.
• Build AI-enabled validation as a real capability, not a demo , by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.

Requirements:

• BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), and 6+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
• Hands-on debug depth across silicon, board, and software boundaries , logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior , with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.
• At least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.
• Demonstrated AI-driven validation workflow you built or scaled, not just used , with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate.

Benefits:

• Competitive benefits
• Flexible time off
• Continuous learning