Senior Engineer, Physical Design

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies. You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus.

What You'll Be Doing

• Drive Place and Route (PnR) implementation for complex semiconductor designs.
• Execute and optimize physical design flows across key stages of the PnR lifecycle.
• Work extensively with Fusion Compiler (FC) and/or Innovus for design implementation.
• Perform and support physical design signoff using methodologies and tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC, or similar.
• Analyze implementation results and identify opportunities for Power, Performance, and Area (PPA) improvement.
• Contribute to continuous improvement of physical design flows, methodologies, and flow usage.
• Debug complex implementation and flow issues using strong analytical and problem-solving skills.
• Collaborate with engineering teams across different functions, geographies, and cultures.
• Explore productivity improvements through modern engineering and AI-assisted tools such as Cursor.

The Impact You Will Have

• Help deliver high-quality physical design implementation for advanced semiconductor designs.
• Improve Power, Performance, and Area (PPA) through design and flow optimization.
• Enhance the efficiency, robustness, and scalability of PnR implementation methodologies.
• Identify and resolve complex physical design and signoff issues.
• Contribute to continuous improvement and automation of implementation flows.
• Enable effective collaboration across global and cross-functional engineering teams.

What You'll Need

• BS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 3+ years of relevant experience, OR
• MS/M.Tech in EE, ECE, or equivalent with 2+ years of relevant experience.
• Strong hands-on experience in PnR design implementation and/or PnR flow methodologies.
• Comprehensive understanding of the PnR development flow.
• Good hands-on experience with Fusion Compiler (FC) or Innovus.
• Good understanding of physical design signoff tools and methodologies.
• Experience or exposure to ICV, RedHawk, PrimeTime, StarRC, or similar tools.
• Experience contributing to PPA improvement and flow optimization activities.
• Strong debugging, analytical, and problem-solving skills.
• Excellent collaboration and influencing skills with the ability to work effectively in cross-cultural, multi-geography, and matrixed teams.
• Exposure to AI-assisted engineering tools such as Cursor is a plus.